1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a semiconductor mesa, and more particularly, it relates to a method of manufacturing a heterojunction bipolar transistor.
2. Description of the Prior Art
A heterojunction bipolar transistor which has specific dimensions of a emitter/base junction being less than that of a collector/base junction, has been widely known in the field of semiconductor devices. The construction and features of the heterojunction bipolar transistor are disclosed in IECEJ Technical Report Vol. 86 No. 227 P. 21, ED86-107 of the Institute of Electronics and Communication Engineers of Japan (IECEJ) for example. Referring to FIG. 1A through FIG. 1H, one of the conventional methods of manufacturing a heterojunction bipolar transistor will be described below.
First, as shown in FIG. 1A, a semiconductor substrate 1 is prepared. Then a collector layer 2, a base layer 3, and an emitter layer 4, are sequentially deposited on an upper surface of the semiconductor substrate 1 by applying epitaxial growth technique. Next, a resist 5 is provided on an entire upper surface of the emitter layer 4. The resist 5 is provided withe a window 10 by applying photolithography to the resist 5. Then, as shown in FIG. 1B, a metallic layer 6 is deposited on an upper surface of a remaining portion of the resist 5 and a bare region 4b of the emitter layer 4 by means of vapor deposition. The resist 5 and the metallic layer 6 on the resist 5 are removed by applying lift-off technique (FIG. 1C). The metallic layer 6 formed on the bare region 4b of the emitter layer 4 is served as an emitter electrode 6a.
Next, as shown in FIG. 1D, a resist 7 is provided on an upper surface of a bare region of the emitter layer 4 and on the emitter electrode 6a. Then, as shown in FIG. 1E, a part of the resist 7 is selectively removed by means of photolithography to eventually form a resist mask 7a which covers an upper and a side surfaces of the emitter electrode 6a. As shown in FIG. 1F, a part of the emitter layer 4 is selectively removed by wet etching process using the resist mask 7a, thus allowing an emitter mesa 4a to be shaped beneath the resist mask 7a. This process is called "emitter-mesa etching". Side-etch effect of the wet-etching process reduces the dimensions of the emitter mesa 4a to be less than those of the resist mask 7a.
Next, as shown in FIG. 1G, metal is supplied from the upper space by means of vapor deposition so that a metallic layer 8 is formed on an upper surface of the resist mask 7a and also on a plane region 3a, which is substantially a part of an upper surface of the base layer 3 which is not covered by the emitter mesa 4a. Since the resist mask 7a functions as a shielding mask, the metallic layer 8 is not formed on a plane region 3b which is positioned just beneath the resist mask 7a. Next, as shown in FIG. 1H, the resist mask 7a and the metallic layer 8 on the resist mask 7a are respectively removed by means of lift-off technique. The metallic layer 8 remaining on the plane region 3a is eventually utilized for a base electrode 8a.
According to the conventional method of manufacturing a heterojunction bipolar transistor described above, the base electrode 8a is formed by way of self-alignment scheme with respect to the emitter mesa 4a. In other words, as shown in FIG. 1G, the resist mask 7a, which is prepared for shaping the emitter mesa 4a, concurrently functions as a mask for vapor deposition of the base electrode 8a. Consequently, a gap between the emitter mesa 4a and the base electrode 8a, i.e., a width of the plane region 3b, can be made narrow. As a result, an emitter-base resistance is reduced so that a high-frequency characteristics of a heterojunction bipolar transistor is improved.
In order to take full advantage of the potential offered by the heterojunction bipolar transistors, dimensions of the emitter mesa 4a, i.e., emitter-base junction capacitance, are required to be minimized. In the wet etching process for shaping the emitter mesa 4a described at FIG. 1F, a width of the emitter mesa 4a is reduced by a side etching effect. However, since a etching rate in a depthwise direction and that in a lateral direction are almost equal to each other, dimensions of the emitter mesa 4a are limited by the dimensions of the resist mask 7a. Nevertheless, due to certain errors implied in the photolithographic processes done twice during those steps described at FIG. 1A and FIG. 1E, any conventional method cannot actually reduce the dimensions of the resist mask 7a. For example, assuming 2 .mu.m-rule lithography, then, a width of about 6 .mu.m is required for the resist mask 7a.
Consequently, since it is quite difficult for any conventional method to reduce the dimensions of the resist mask 7a, any conventional method is obliged to incur substantial difficulty to securely minimize the dimensions of the emitter mesa 4a.